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128Kx8 Autostore nvSRAM With Real-Time Clock FEATURES
* nvSRAM Combined With Integrated Real-Time Clock Functions (RTC, Watchdog Timer, Clock Alarm, Power Monitor) * Capacitor or Battery Backup for RTC * 25, 45 ns Read Access & R/W Cycle Time * Unlimited Read/Write Endurance * Automatic Non-volatile STORE on Power Loss * Non-Volatile STORE Under Hardware or Software Control * Automatic RECALL to SRAM on Power Up * Unlimited RECALL Cycles * 200K STORE Cycles * 20-Year Non-volatile Data Retention * Single 3 V +20%, -10% Power Supply * Commercial and Industrial Temperatures * 48-pin 300-mil SSOP Package (RoHS-Compliant)
STK17TA8
DESCRIPTION
The Simtek STK17TA8 combines a 1Mb non-volatile static RAM (nvSRAM) with a full-featured real-time clock in a reliable, monolithic integrated circuit. The 1Mbit nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic minutes, hours, or days alarms. There is also a programmable watchdog timer for processor control.
BLOCK DIAGRAM
Quantum Trap 1024 X 1024 ROW DECODER STORE STATIC RAM ARRAY 1024 X 1024 RECALL VCC VCAP VRTCbat VRTCcap
A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
POWER CONTROL STORE/ RECALL CONTROL
HSB
SOFTWARE DETECT INPUT BUFFERS COLUMN I/O COLUMN DEC RTC
A15 - A0
X1 X2 INT A16 - A0
G E W
A0 A 1 A 2 A 3 A 4 A10 A11 MUX
This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status.
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STK17TA8
Packages
VCAP A16 A14 A12 A7 A6 A5 INT A4 NC NC NC VSS NC VRTCbat DQ0 A3 A2 A1 A0 DQ1 DQ2 X1 X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 VCC A15 HSB W A13 A8 A9 NC A11 NC NC NC VSS NC VRTCcap DQ6 G A10 E DQ7 DQ5 DQ4 DQ3 VCC
(TOP)
38 37 36 35 34 33 32 31 30 29 28 27 26 25
For detailed package size specifications, see page 26.
48-Pin SSOP
PIN DESCRIPTIONS
Pin Name A16-A0 DQ7-DQ0 E W G X1 X2 VRTCcap VRTCbat VCC HSB Input I/O Input Input Input Output Input Power Supply Power Supply Power Supply I/O I/O Description Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array or one of 16 bytes in the clock register map Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC Chip Enable: The active low E input selects the device Write Enable: The active low W enables data on the DQ pins to be written to the address location selected on the falling edge of E Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. Crystal Connection, drives crystal on startup Crystal Connection for 32.768 kHz crystal Capacitor supplied backup RTC supply voltage (Left unconnected if VRTCbat is used) Battery supplied backup RTC supply voltage (Left unconnected if VRTCcap is used) Power: 3.0V, +20%, -10% Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor. Programmable to either active high (push/pull) or active low (open-drain) Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. Ground Unlabeled pins have no internal connections.
INT VCAP VSS (Blank)
Output Power Supply Power Supply No Connect
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SSOP
STK17TA8
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to Ground . . . . . . . . . . . . . -0.5V to 4.1V Voltage on Input Relative to VSS . . . . . . . . . .-0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .-0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-55C to 125C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-55C to 140C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
jc 6.2 C/W; ja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC1 PARAMETER MIN Average VCC Current 65 50 70 55 mA mA MAX MIN MAX INDUSTRIAL UNITS
(VCC = 2.7V-3.6V)
NOTES
tAVAV = 25ns tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care, VCC = max Average current for duration of STORE cycle (tSTORE) W (V CC - 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care Average current for duration of STORE cycle (tSTORE) E (VCC -0.2V) All Others VIN 0.2V or (VCC-0.2V) Standby current level after nonvolatile cycle complete VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 2mA (except HSB) IOUT = 4mA
ICC2
Average VCC Current during STORE 3 Average VCC Current at tAVAV = 200ns 3V, 25C, Typical 10 10 mA 3 mA
ICC3
ICC4
Average VCAP Current during AutoStoreTM Cycle VCC Standby Current (Standby, Stable CMOS Levels)
3
3
mA
ISB
3
3
mA
IILK IOLK VIH VIL VOH VOL TA VCC VCAP NVC DATAR
Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature Operating Voltage Storage Capacitance Nonvolatile STORE operations Data Retention 0 2.7 17 200 20 2.0 VSS -0.5 2.4
1 1 VCC + 0.5 0.8 2.0 VSS -0.5 2.4 0.4 70 3.6 57 -40 2.7 17 200 20
1 1 VCC + 0.5 0.8
A A V V V
0.4 85 3.6 57
V C V F K Years
3.0V +20%, -10% Between VCAP pin and VSS, 5V rated.
@ 55 deg C
Note: The HSB pin has IOUT=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested. Note: The INT pin is open-drain and does not source or sink high current when Interrupt Register bit D3 is low.
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STK17TA8
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2
CAPACITANCEb
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 7 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
Note b: These parameters are guaranteed but not tested.9,9 /
3.0V
577 Ohms OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE
Figure 1: AC Output Loading
3.0V
577 Ohms OUTPUT 789 Ohms 5 pF INCLUDING SCOPE AND FIXTURE
Figure 2: AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)
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STK17TA8
RTC DC CHARACTERISTICS
Symbol Parameter
RTC Backup Current RTC Battery Pin Voltage RTC Capacitor Pin Voltage RTC Oscillator time to start
Commercial Min Max
-- 1.8 1.2 -- -- 300 3.3 2.7 10 5
Industrial Min Max
-- 1.8 1.2 -- -- 350 3.3 2.7 10 5
Units
nA V V sec sec
Notes
From either VRTCcap or VRTCbat Typical = 3.0 Volts during normal operation Typical = 2.4 Volts during normal operation @ MIN Temperature from Power up or Enable @ 25C from Power up or Enable
IBAK VRTCbat VRTCcap tOSCS
RTC RECOMMENDED COMPONENT CONFIGURATION
C1 RF C2
Y1
X1 X2
Recommended Values Y1 = 32.768 KHz RF = 10M Ohm C1 = 0 (install cap footprint, but leave unloaded) C2 = 56 pF 10% (do not vary from this value)
Figure 3. RTC Component Configuration
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STK17TA8
SRAM READ CYCLES #1 & #2
SYMBOLS NO. #1 #2 Alt. PARAMETER MIN MAX MIN MAX STK17TA8-25 STK17TA8-45 UNITS
1 2 3 4 5 6 7 8 9 10 11 tAXQXd tAVAVc tAVQVd
tELQV tELEHc tAVQVd tGLQV tAXQXd tELQX tEHQZe tGLQX tGHQZe tELICCLb tEHICCHb
tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS
Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Address Change or Chip Enable to Output Active Address Change or Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 0 3 3 25
25 45 25 12 3 3 10 0 10 0 25
45
ns ns
45 20
ns ns ns ns ns ns
15
15
ns ns
45
ns
Note c: Note d: Note e: Note f:
W must be high during SRAM READ cycles. Device is continuously selected with E and G both low Measured 200mV from steady state output voltage. HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2 tAVAV ADDRESS 5 3 tAVQV
DATA VALID
tAXQX DQ (DATA OUT)
SRAM READ CYCLE #2: E and G Controlledc,f
ADDR ESS t E LE H 1 tEL Q V
2
tEHAX 11 tEHI CC L 7 tEHQ Z
29
E
27
t ELQ X
6
G
t AV QV 4 t G L QV 9 tGH Q Z
3
8 tG L Q X DQ (DATA OUT) 10 tELI CC H
DAT A VAL ID
AC T IVE
ICC
ST AND BY
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STK17TA8
SRAM WRITE CYCLES #1 & #2
SYMBOLS NO. #1 #2 Alt. PARAMETER MIN MAX MIN MAX STK17TA8-25 STK17TA8-45 UNITS
12 13 14 15 16 17 18 19 20 21
tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX t WLQZ
e, g
tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
25 20 20 10 0 20 0 0 10 3
45 30 30 15 0 30 0 0 15 3
ns ns ns ns ns ns ns ns ns ns
tWHQX
Note g: If W is low when E goes low, the outputs remain in the high-impedance state. Note h: E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledg,h
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE DATA VALID
19 tWHAX
tAVWL W
18
16 tWHDX
20
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledg,h
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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STK17TA8
AutoStoreTM/POWER-UP RECALL
SYMBOLS NO. Standard Alternate PARAMETER MIN MAX STK17TA8 UNITS NOTES
22 23 24 25
tHRECALL tSTORE VSWITCH VCCRISE tHLHZ
Power-up RECALL Duration
STORE Cycle Duration
40 12.5 2.65 150
ms ms V
S
i j,k
Low Voltage Trigger Level VCC Rise Time
Note i: tHRECALL starts from the time VCC rises above VSWITCH Note j: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place Note k: Industrial Grade Devices require 15 ms MAX.
AutoStoreTM/POWER-UP RECALL
STORE occurs only if a SRAM write has happened. VCC 24 VSWITCH No STORE occurs without at least one SRAM write.
25 tVCCRISE
AutoStoreTM
23 tSTORE
23 tSTORE
POWER-UP RECALL
22 tHRECALL
22 tHRECALL
Read & Write Inhibited
POWER-UP RECALL
BROWN OUT TM AutoStore
POWER-UP RECALL
POWER DOWN TM AutoStore
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
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STK17TA8
SOFTWARE-CONTROLLED STORE/RECALL CYCLEl,m
Symbols NO. E Cont G Cont Alternate PARAMETER MIN STORE / RECALL Initiation Cycle Time MAX MIN MAX STK17TA8-35 STK17TA8-45 UNITS NOTES
26 27 28 29 30
tAVAV tAVEL tELEH tEHAX tRECALL
tAVAV tAVGL tGLGH tGHAX tRECALL
tRC tAS tCW
25 0 20 1 100
45 0 30 1 100
ns ns ns ns
s
m
Address Set-up Time Clock Pulse Width Address Hold Time
RECALL Duration
Note l: The software sequence is clocked on the falling edge of E controlled READs or G controlled READs Note m: The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDm
26 tAVAV ADDRESS 27 tAVEL
ADDRESS #1
26 tAVAV
ADDRESS #6
E
28 tELEH
29 tEHAX
G
23 tSTORE DQ (DATA)
DATA VALID DATA VALID
/t
30
RECALL
HIGH IMPEDENCE
SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDm
26 tAVAV ADDRESS
ADDRESS #1
26 tAVAV
ADDRESS #6
E
27 tAVGL
28 tGLGH
G
23 tSTORE
29 tGHAX DQ (DATA)
DATA VALID DATA VALID
/
30 tRECALL
HIGH IMPEDENCE
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STK17TA8
HARDWARE STORE CYCLE
SYMBOLS PARAMETER Standard Alternate MIN MAX STK17TA8 UNITS NOTES
31 1 32 2
tDELAY tHLHX
tHLQZ
Hardware STORE to SRAM Disabled Hardware STORE Pulse Width
1 15
70
s
n
ns
Note n: On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete
HARDWARE STORE CYCLE
32 tHLHX
HSB (IN)
23 tSTORE
HSB (OUT)
31 tDELAY DQ (DATA OUT)
SRAM Enabled SRAM Enabled
Soft Sequence Commands
NO. SYMBOLS Standard PARAMETER STK17TA8 MIN Soft Sequence Processing Time MAX UNITS NOTES
34 34 1
tSS
70
s
o,p
Notes: o: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. p: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
34 tss
Soft Sequence Command ADDRESS
ADDRESS #1 ADDRESS #6
34 tss
Soft Sequence Command
ADDRESS #1 ADDRESS #6
Vcc
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STK17TA8
MODE SELECTION
E
H L L
W
X H L
G
X L X
A16-A0
X X X 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08FC0 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63
Mode
Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall
I/O
Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Power
Standby Active Active
Notes
L
H
L
Active
q,r,s
ICC2
L
H
L
Active
q,r,s
Notes q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. r: While there are 17 addresses on the STK17TA8, only the lower 16 are used to control software modes s: I/O state depends on the state of G. The I/O table shown assumes G low
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STK17TA8 nvSRAM OPERATION
nvSRAM
The STK17TA8 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK17TA8 supports unlimited read and writes like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
AutoStore OPERATION
The STK17TA8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). AutoStore operation, a unique feature of Simtek QuanumTrap technology is a standard feature on the STK17TA8. During normal operation, the device will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 4 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of the capacitor. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation
SRAM READ
The STK17TA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-16 determine which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W and HSB is brought low.
VCC
10k Ohm
VCAP
VCC
VCAP
W
Figure 4: AutoStore Mode
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STK17TA8
has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. To initiate the software STORE cycle, the following READ sequence must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F Valid READ Valid READ Valid READ 0xB1C7 Valid READ 0x7C1F Valid READ 0x8FC0 Initiate STORE Cycle
HARDWARE STORE (HSB) OPERATION
The STK17TA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK17TA8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pullup and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK17TA8 will continue to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. If HSB is not used, it should be left unconnected.
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence and that G is active. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled or G controlled READ operations must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x4C63 Valid READ Valid READ Valid READ Initiate RECALL Cycle 0xB1C7 Valid READ 0x7C1F Valid READ
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition (VCCSOFTWARE STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK17TA8 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. Once a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed.
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM will once again be ready for READ or WRITE operations. The RECALL operation in no way alters the data in the nonvolatile storage elements.
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STK17TA8
DATA PROTECTION
The STK17TA8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The lowvoltage condition is detected when VCCNOISE CONSIDERATIONS
The STK17TA8 is a high-speed memory and so must have a high-frequency bypass capacitor of 0.1 F connected between both VCC pins and VSS ground plane with no plane break to chip VSS. Use leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise.
PREVENTING AUTOSTORE
Because of the use of nvSRAM to store critical RTC data, the AutoStore function can not be disabled on the STK17TA8.
BEST PRACTICES
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: * The non-volatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites will sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
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STK17TA8
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK17TA8 with the benefit of power supply current that scales with cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns. Figure 4 shows the relationship between ICC and READ/ WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK17TA8 depends on the following items: 1. 2. 3. 4. 5. 6. The duty cycle of chip enable. The overall cycle rate for accesses. The ration of READs to WRITEs. The operating temperature. The VCC level. I/O loading.
Figure 5- Current vs Cycle Time
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STK17TA8 RTC OPERATION
REAL TIME CLOCK
The clock registers maintain time up to 9,999 years in one second increments. The user can set the time to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions which are used to set time with a write cycle and to read time during a read cycle. These registers contain the Time of Day in BCD format. Bits defined as "0" are currently not used and are reserved for future use by Simtek. You can power the real time clock with either a capacitor or a battery. Factors to be considered when choosing a backup power source include the expected duration of power outages and the cost & reliability trade-off of using a battery versus a capacitor. If you select a capacitor power source, connect the capacitor to the VRTCcap pin and leave the VRTCbat pin unconnected. Capacitor backup time values based on maximum current specs are shown below. Nominal times are approximately 3 times longer.
Capacitor Value 0.1 F 0.47 F 1.0 F Backup Time 72 hours 14 days 30 days
READING THE CLOCK
The user should halt internal updates to the real time clock registers before reading clock data to prevent the reading of data in transition. Stopping the internal register updates does not affect clock accuracy. Write a "1" to the read bit "R" (in the Flags register at 0x1FFF0) will capture the current time in holding registers. Clock updates will not restart until a "0" is written to the read bit. The RTC registers can then be read while the internal clock continues to run. Within 20ms after a "0" is written to the read bit, all real time clock registers are simultaneously updated.
A capacitor has the obvious advantage of being more reliable and not containing hazardous materials. The capacitor is recharged every time the power is turned on so that real time clock continues to have the same backup time over years of operation. If you select a battery power source, connect the battery to the VRTCbat pin and leave the VRTCcap pin unconnected. A 3V lithium battery is recommended for this application. The battery capacity should be chosen for the total anticipated cumulative downtime required over the life of the system. The real time clock is designed with a diode internally connected to the VRTCbat pin. This prevents the battery from ever being charged by the circuit.
SETTING THE CLOCK
Set the write bit "W" (in the Flags register at 0x1FFF0) to a "1" to enable the time to be set. The correct day, date and time can then be written into the real time clock registers in 24-hour BCD format. The time written is referred to as the "Base Time." This value is stored in non-volatile registers and used in calculation of the current time. Reset the write bit to "0" to transfer the time to the actual clock counters. The clock will start counting at the new base time.
STOPPING AND STARTING THE RTC OSCILLATOR
The OSCEN bit in Calibration register at 0x1FFF8 enables RTC oscillator operation. This bit is non-volatile and shipped to customers in the "enabled" state (set to 0). OSCEN should be set to a 1 to preserve battery life while the system is in storage. This will turn off the oscillator circuit extending the battery life. If the OSCEN bit goes from disabled to enabled, it will typically take 5 seconds (10 seconds max) for the oscillator to start.
BACKUP POWER
The RTC in intended to keep time even when system power is lost. When primary power, VCC, drops below VSWITCH, the real time clock will switch to the backup power supply connected to either the VRTCcap or VRTCbat pin. The clock oscillator uses a maximum of 300 nanoamps at 2 volts to maximize the backup time available from the backup source.
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The STK17TA8 has the ability to detect oscillator failure due to loss of backup power. The failure is recorded by the OSCF (Oscillator Failed) bit of the Flags register (at address 0x1FFF0). When the device is powered on (VCC goes above VSWITCH), the OSCEN bit is checked for "enabled" status. If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms, the OSCF bit is set. The user should check for this condition and then write a 0 to clear the flag. When the OSCF flag bit is set, the real time clock registers are reset to the "Base Time" (see the section "Setting the Clock"), the value last written to the real time clock registers. The value of OSCF should be reset to 0 when the real time clock registers are written for the first time. This will initialize the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit "W" (in the Flags register at 0x1FFF0) to a "1" to enable writes to the Flag register. Write a "0" to the OSCF bit. and thenreset the write bit to "0" to disable writes. so on. Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles. That is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. The calibration register value is determined during system test by setting the CAL bit in the Flags register (at 0x1FFF0) to 1. This causes the INT pin to toggle at a nominal 512 Hz. This frequency can be measured with a frequency counter. Any deviation measured from the 512 Hz will indicate the degree and direction of the required correction. For example, a reading of 512.01024 Hz would indicate a +20 ppm error, requiring a -10 (001010) to be loaded into the Calibration register. Note that setting or changing the calibration register does not affect the frequency test output frequency. To set or clear CAL, set the write bit "W" (in the Flags register at 0x1FFF0) to a "1" to enable writes to the Flag register. Write a value to CAL. and then reset the write bit to "0" to disable writes. The default Calibration register value from the factory is 00h. The user calibration value loaded is retained during a power loss.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator with a nominal frequency of 32.768 KHz. Clock accuracy will depend on the quality of the crystal, specified (usually 35 ppm at 25 C). This error could equate to 1.53 minutes gain or loss per month. The STK17TA8 employs a calibration circuit that can improve the accuracy to +1/-2 ppm at 25 C. The calibration circuit adds or subtracts counts from the oscillator divider circuit. The number of time pulses are added or substracted depends upon the value loaded into the five calibration bits found in Calibration register (at 0x1FFF8). Adding counts speeds the clock up; subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits of the register. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit, where a "1" indicates positive calibration and a "0" indicates negative calibration. Calibration occurs during a 64 minute period. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary "1" is loaded into the register, only the first 2 minutes of the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and
ALARM
The alarm function compares a user-programmable alarm time/date (stored in registers 0x1FFF1-5) with the real time clock time-of-day/date values. When a match occurs, the alarm flag (AF) is set and an interrupt is generated if the alarm interrupt is enabled. The alarm flag is automatically reset when the Flags register is read. Each of the alarm registers has a match bit as its MSB. Setting the match bit to a 1 disables this alarm register from the alarm comparison. When the match bit is 0, the alarm register is compared with the equivalent real time clock register. Using the match bits, the alarm can occur as specifically as one particular second on one day of the month or as frequently as once per minute. Note: The product requires the match bit for seconds(1x1FFF2 - D7) be set to 0 for proper operation of the Alarm Flag and Interrupt. The alarm value should be initialized on power-up by software since the alarm registers are not non-volatile.
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To set or clear Alarm registers, set the write bit "W" (in the Flags register at 0x1FFF0) to a "1" to enable writes to the Alarm registers. Write an alarm value to the alarm registers and then reset the write bit to "0" to disable writes. When the power supply drops below VSWITCH, the real time clock circuit is switched to the backup supply (battery or capacitor) . When operating from the backup source, no data may be read or written to the nvSRAM and the clock functions are not available to the user. The clock continues to operate in the background. Updated clock data is available to the user tHRECALL delay after VCC has been restored to the device. When power is lost, the PF flag in the Flags Register is set to indicate the power failure and an interrupt is generated if the power fail interrupt is enabled (interrupt register=20h). This line would normally be tied to the processor master reset input for perform power-off reset.
WATCHDOG TIMER
The watchdog timer is designed to interrupt or reset the processor should the program get hung in a loop and not respond in a timely manner. The software must reload the watchdog timer before it counts down to zero to prevent this interrupt or reset. The watchdog timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The watchdog timer function does no operate unless the oscillator is running. The watchdog counter is loaded with a starting value from the load register and then counts down to zero setting the watchdog flag (WDF) and generating an interrupt if the watchdog interrupt is enabled. The watchdog flag bit is reset when the flag register is read. The operating software would normally reload the counter by setting the watchdog strobe bit (WDS) to 1 within the timing interval programmed into the load register. To use the watchdog timer to reset the processor on timeout, the INT is tied to processor master reset and Interrupt register is programmed to 24h to enable interrupts to pulse the reset pin on timeout. To load the watch dog timer, set a new value into the load register by writing a "0" to the watchdog write bit (WDW) of the watchdog register (at 01x1FFF7). Then load a new value into the load register. Once the new value is loaded, the watchdog write bit is then set to 1 to disable watchdog writes. The watchdog strobe bit (WDS) is then set to 1 to load this value into the watchdog timer. Note: Setting the load register to zero will disable the watchdog timer function. The system software should initialize the watchdog load register on power-up to the desired value since the register is not non-volatile.
INTERRUPTS
The STK17TA8 has a Flags register, Interrupt Register, and interrupt logic that can interrupt a microcontroller or generate a power-up master reset signal. There are three potential interrupt sources: the watchdog timer, the power monitor, and the clock alarm. Each can be individually enabled to drive the INT pin by setting the appropriate bit in the Interrupt register. In addition, each has an associated flag bit in the Flags register that the host processor can read to determine the interrupt source. Two bits in the Interrupt register determine the operation of the INT pin driver. A functional diagram of the interrupt logic is shown below.
WDF Watchdog Timer WIE PF Power Monitor VINT AF Clock Alarm AIE PFE P/L Pin Driver H/L VSS VCC INT
Figure 6. Interrupt Block Diagram
POWER MONITOR
The STK17TA8 provides a power monitor function. The power monitor is based on an internal band-gap reference circuit that compares the VCC voltage to VSWITCH.
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INTERRUPT REGISTER Watchdog Interrupt Enable (WIE). When set to 1, the watchdog timer drives the INT pin when a watchdog time-out occurs. When WIE is set to 0, the watchdog time-out only sets the WDF flag bit. Alarm Interrupt Enable (AIE). When set to 1, the INT pin is driven when an alarm match occurs. When set to 0, the alarm match only sets the AF flag bit. Power Fail Interrupt Enable (PFE). When set to 1, the INT pin is driven by a power fail signal from the power monitor circuit. When set to 0, only the PF flag is set. High/Low (H/L). When set to a 1, the INT pin is active high and the driver mode is push-pull. The INT pin can drive high only when VCC>VSWITCH. When set to a 0, the INT pin is active low and the drive mode is open-drain. The active low (open drain) output is maintained even when power is lost . Pulse/Level (P/L). When set to a 1, the INT pin is driven for approximately 200 ms when an interrupt occurs. The pulse is reset when the Flags register is read. When P/L is set to a 0, the INT pin is driven high or low (determined by H/L) until the Flags register is read. The Interrupt register is loaded with the default value 00h at the factory. The user should configure the Interrupt register to the value desired for their desired mode of operation. Once configured, the value is retained during power failures.
FLAGS REGISTER
The Flags register has three flag bits: WDF, AF, and PF. These flags are set by the watchdog time-out, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts to be informed when a flag is set. The flags are automatically reset once the register is read. The Flags register is automatically loaded with the value 00h on power up (with the exception of the OSCF bit).
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RTC Register
Register 0x1FFFF 0x1FFFE 0x1FFFD 0x1FFFC 0x1FFFB 0x1FFFA 0x1FFF9 0x1FFF8 0x1FFF7 0x1FFF6 0x1FFF5 0x1FFF4 0x1FFF3 0x1FFF2 0x1FFF1 0x1FFF0 WDF 0 0 0 0 0 0 OSCEN [0] WDS WIE [0] M M M M 0 WDW AIE [0] 0 0 PFE [0] 0 H/L [1] BCD Format Data D7 D6 D5 D4 10s Months D3 D2 D1 Years Months Day of Month 0 Day of Week Hours Minutes Seconds Calibration[00000] WDT P/L [0] 0 0 D0 10s Years 0 0 0 0 0 Function / Range Years: 00-99 Months: 01-12 Day of Month: 0131 Day of week: 01-07 Hours: 00-23 Minutes: 00-59 Seconds: 00-59 Calibration values* Watchdog* Interrupts* Alarm, Day of Month: 01-31 Alarm, hours: 0023 Alarm, minutes: 0059 Alarm, seconds: 00-59 Centuries: 00-99 R[0] Flags*
10s Day of Month 0 10s Minutes 10s Seconds Cal Sign 0 10s Hours
10s Alarm Date 10s Alarm Hours
Alarm Day Alarm Hours Alarm Minutes Alarm Seconds Centuries
10 Alarm Minutes 10 Alarm Seconds 10s Centuries AF PF OSCF 0
CAL[0]
W[0]
* A binary value, not a BCD value. 0 - Not implemented, reserved for future use. Default Settings of non-volatile Calibration and Interrupt registers from factory Calibration Register=00h Interrupt Register=00h The User should configure to desired value at startup or during operation and the value is then retained during a power failure. [ ] designates values shipped from the factory. See STOPPING AND STARTING THE RTC OSCILLATOR on page 16.
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Register Map Detail 0x1FFFF
D6 D5 D1 D0 10s Years Years Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. D7 Real Time Clock - Years D4 D3 D2
0x1FFFE
Real Time Clock - Months D7 D6 D5 D4 D3 D2 D1 D0 10s 0 0 0 Months Month Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12.
0x1FFFD
Real Time Clock - Date D7 D6 D5 D4 D3 D2 D1 D0 0 0 10s Day of month Day of month Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Leap years are automatically adjusted for.
0x1FFFC
Real Time Clock - Day D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Day of week Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date.
0x1FFFB
Real Time Clock - Hours D7 D6 D5 D4 D3 D2 D1 D0 0 0 10s Hours Hours Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23.
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0x1FFFA
Real Time Clock - Minutes D7 D6 D5 D4 D3 D2 D1 D0 0 10s Minutes Minutes Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Real Time Clock - Seconds D7 D6 D5 D4 D3 D2 D1 D0 0 10s Seconds Seconds Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59.
0x1FFF9
0x1FFF8
OSCEN Calibration Sign Calibration
D5 D2 D1 D0 Calibrat OSCEN 0 Calibration ion Sign Oscillator Enable. When set to 1, the oscillator is disabled. When set to 0, the oscillator is enabled. Disabling the oscillator saves battery/capacitor power during storage. Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. These five bits control the calibration of the clock.
D7
D6
Calibration D4 D3
0x1FFF7
WDS
WDW
WDT
Watchdog Timer D7 D6 D5 D4 D3 D2 D1 D0 WDS WDW WDT Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0. Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out value (WDT5-WDT0). This allows the user to strobe the watchdog stobe bit without disturbing the time-out value. Set this bit to 0 to allow bits 5-0 to be written. Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of time-out values is 31.25 ms (a setting of 1) to 2 seconds (setting of 3Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was cleared to 0 on a previous cycle.
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0x1FFF6
Interrupt D7 D6 D5 D4 D3 D2 D1 D0 WIE AIE PFIE ABE H/L P/L 0 0 Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the INT pin as well as setting the WDF flag. When set to 0, the watchdog time-out only sets the WDF flag. Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as setting the AF flag. When set to 0, the alarm match only affects the AF flag. Power-Fail Enable. When set to 1, a power failure drives the INT pin as well as setting the PF flag. When set to 0, the power failure only sets the PF flag. Reserved For Future Used High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open drain, active low. Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags register is read. Alarm - Day D7 D6 D5 D4 D3 D2 D1 D0 M 0 10s Alarm Date Alarm Date Contains the alarm value for the date of the month and the mask bit to select or deselect the date value. Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the date value.
WIE AIE PFIE 0 H/L P/L
0x1FFF5
M
0x1FFF4
M
Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 M 0 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value.
0x1FFF3
M
D7 D6 D5 D2 D1 D0 M 10s Alarm Minutes Alarm Minutes Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the minutes value.
Alarm - Minutes D4 D3
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0x1FFF2
Alarm - Seconds D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Seconds Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds' value. Match. Setting this bit to 0 causes the seconds' value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value.
M
0x1FFF1
Real Time Clock - Centuries D7 D6 D5 D4 D3 D2 D1 D0 10s Centuries Centuries Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.
0x1FFF0
D7 WDF
D6 AF
D5 PF
Flags D4 D3 OSCF 0
D2 CAL
D1 W
D0 R
WDF
AF PF OSCF
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power-up. Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power-up. Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold VSWITCH. It is cleared to 0 when the Flags register is read or on power-up. Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is enabled and not running in the first 5ms of operation. This indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0 to clear this condition. Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When set to 0, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up. Write Enable. Setting the W bit to 1 freezes updates of the RTC registers and enables writes to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of the RTC registers to be transferred to the timekeeping counters if the time has been changed (a new base time is loaded). This bit defaults to 0 on power up. Read Time. Set R to 1 to captures the current time in holding registers so that clock updates are not seen during the reading process. Set R to 0 to enable the holding register to resume clock updates. This bit defaults to 0 on power up.
CAL
W
R
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ORDERING INFORMATION STK17TA8-R F 45 I TR
Packing Option Blank=Tube TR= Tape and Reel Temperature Range Blank=Commercial (0 to +70 C) I= Industrial (-45 to +85 C) Access Time 25=25 ns 45=45 ns Lead Finish F=100% Sn (Matte Tin) RoHS Compliant Package R=Plastic 48-pin 300 mil SSOP (25 mil pitch)
ORDERING CODES
Part Number STK17TA8-RF25 STK17TA8-RF45 STK17TA8-RF25TR STK17TA8-RF45TR STK17TA8-RF25I STK17TA8-RF45I STK17TA8-RF25ITR STK17TA8-RF45ITR Description 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300 Access Times 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time Temperature Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
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STK17TA8 PACKAGE DIAGRAMS
48 Pin SSOP
TOP VIEW
N
0.620 15.75 0.630 16.00
(
) BOTTOM VIEW
0.400 0.410
( 10.16 ) 10.41
0.292 0.299 7.42 ( 7.59 ) 0.292 0.299 7.42 ( 7.59 )
.045 .055
(11.43) 13.97
Pin 1 indicator .045 DIA. (11.43)
1 2 3
.020 (5.1)
.035 .045
8.89 (11.43)
SIDE VIEW
0.025 (0.635) 0.008 0.0135
(
0.203 0.343
)
0.095 0.110
END VIEW
0.010 0.016
( 0.25 ) 0.41
45
( 2.41) 2.79
SEATING PLANE
0.088 0.092
( 2.24 ) 2.34
SEE DETAIL A
0.620 15.75 0.630 16.00
(
)
0.008 0.016
( 0.20) 0.41
DIM = INCHES
MIN MAX
0.010 (0.25)
DETAIL A END VIEW
PARTING LINE
GAUGE PLANE SEATING PLANE
DIM = mm
(
MIN MAX
)
0 8 0.024 0.040
( 0.61 ) 1.02
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Document Revision History
Rev 0.0 0.1 0.2 Date February 2003 March 2003 June 2003
Publish New Datasheet Remove 525 mil SOIC, Add 48-pin SSOP and 40-pin DIP packages, Modify block diagram in AutoStore description section Modify 600 mil DIP pin-out (switch pins 32 and 33), Update Power-up Recall specs, Update Software Controlled Store/Recall Cycle, Added Hardware Store Description, Modified Mode Selection Table, Updated VSWITCH, Updated tSTORE, Modify IBAK and VBAK Change part number from STK17CA8 to STK17TA8; Add lead-free finish option
Change
0.3 1.0
February 2004 December 2004
Parameter VCAP Min tVCCRISE ICC1 Max Com. ICC1 Max Com. ICC1 Max Com. ICC1 Max Ind. ICC1 Max Ind. ICC1 Max Ind. ICC2 Max ICC4 Max tHRECALL tSTORE tRECALL tGLQV
Old Value 10uF NA 35 mA 40 mA 50 mA 35 mA 45 mA 55 mA 1.5 mA 0.5 mA 5 ms 10 ms 20 us 10 ns
New Value 17uF 150 us 50 mA 55 mA 65 mA 55 mA 60 mA 70 mA 3.0 mA 3.0 mA 20 ms 12.5 ms 40 us 12 ns
Notes New Spec 45 ns access 35 ns access 25 ns access 45 ns access 35 ns access 25 ns access Com. & Ind. Com. & Ind.
25 ns device
1.1
April 2005
Changed RTC Register unused bits "X" to require zero "0" value when writing values
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Rev 1.2 Date September 2005
Parameter ICC3 Max Com. ICC3 Max Ind. ISB Max Com. ISB Max Ind. tRECALL tSTORE Max STORE Cycles tOSCS tOSCS C1 C2
Change
Old Value 5 mA 5 mA 2 mA 2 mA 40 us 12.5 ms 6 1x10 1 min 10 sec 2.2 pf 47 pf New Value 10 mA 10 mA 3 mA 3 mA 60 us 15.0 ms 5 5x10 10 sec 5 sec 0 pf 56 pf Notes
Soft Recall Industrial Grade Only Contact Simtek for details @ Min. Temp @ 25 deg C from Power U RTC Output Cap. RTC Input Cap.
Removed Plastic DIP 40-pin package offering. Package type "W"
1.3
December 2005
Parameter tRECALL tSS DATAR
Old Value 60 s Undefined 100 Years at unspecified temperature
New Value 100 s 70 s 20 Years @ Max Temperature
Notes Soft Recall New Spec New Data Retention Specification
Discontinued 35 ns speed grade option.
1.4
July 2006
Parameter tHRECALL NVC DATAR VSWITCH Min.
Old Value 20 ms 500K 20 Years @ 85 C 2.55 V
New Value 40 ms 200K 20 Years @ 55 C
Notes Power-up RECALL Duration New Nonvolatile Store Cycle Spec New Data Retention Spec No Min. Spec
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Rev 1.5 Date March 2007
Parameter IOUT for HSB tELAX tGLAX tEHAX tGHAX tDELAY Max. tHLBL tSS Old Value No spec 20, 30 ns 20, 30 ns No spec No spec No spec 300 ns 70 s min
Change
New Value -10 A No spec No spec 1 ns 1 ns 70 s max No spec 70 s max Notes Added as note Replace by tEHAX Replace by tGHAX Address hold required Address hold required HSB drives low immediately Wrong spec
ABE bit removed from Interrupt Register Interrupt Register Initializes to 00h Flag Bits(WDF, AF, PF) Initialize to Zero W-bit in Flag Register Enables Writes To RTC, Alarm, Calibration, Interrupt, and Flag Registers Add Tape & Reel Ordering Option Add Product Ordering Code Listing Add Package Drawings Reformat Entire Document
2.0
January 2008
Page 3: added thermal characteristics. For DC characteristics, Page 5: revised recommended value verbiage. Page 6: in the SRAM Read Cycles #1 and #2 table, revised parameter description for tELQX and tEHQZand changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing diagram and changed title to add G controlled. Page 9: revised the notes below the Software-Controlled Store/Recall Cycle diagram. Page 11: in the Mode Selection table, changed column to A16-A0 and added a 0 after all instances of "0x". Page 12: under AutoStore Operation, revised text to read: "Refer to the DC CHARACTERISTICS table for the size of the capacitor." Page 13: under Hardware Store (HSB) Operation, revised first paragraph to read "The HSB pin has a very resistive pullup..." Page 14: added best practices section. Revised RTC register map for registers 0x1FFF8 (D7) and 0x1FFF6 (D7, D6, D5, D3, and D2). Page 25: added access times column to the Ordering Codes.
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